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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
INTRODUCTION
The KB8821/22/23 are high performance dual frequency synthesizers with integrated prescalers designed for RF operation up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz. The KB8821/22/23 contain dual-modulus prescalers. The RF synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or 64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or a 16/17 prescaler. Using a proprietary digital phase-locked-loop technique, the KB8821/22/23 have linear phase detector characteristic and can be used for very stable, low noise local oscillator signal. Supply voltage can range from 2.7V to 4.0V. The KB8821/22/ 23 are now available in a 20-TSSOP/24-QFN package.
20-TSSOP-225
KB8821/22/23
ORDERING INFORMATION
Device KB8821/22/23 KB8821/22/23 Package 24-QFN* Tem. Range -40 ~ +85C 20-TSSOP-225 -40 ~ +85C
FEATURES
* Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA) * Operating voltage range : 2.7 ~ 4.0V * Selectable power saving mode(Icc=1uA typical @3V) * Dual modulus prescaler :
KB8821/22 KB8823 KB8821/22/23 (RF) 64/65 or 128/129 (RF) 32/33 or 64/65 (IF) 8/9 or 16/17
* QFN : Quad Flat Non-leaded(see Addendum).
APPLICATIONS
* Cellular telephone systems : KB8821 * Portable wireless communications : KB8822 (PCS/PCN, cordless) * Wireless Local Area Networks (W-LANs) : KB8823 * Other wireless communication systems
* Programmability via serial bus interface * No dead-zone PFD * Variable charge pump output current * High speed lock mode
BLOCK DIAGRAM
finRF finRF + RF Prescaler RF N Counter RF Phase Detector RF LD CLOCK LE DATA Serial Data Control foLD Data Out Multiplexer foLD RF Charge Pump CPoRF
RF R Counter OSCin IF R Counter finIF finIF + IF Prescaler IF N Counter IF Phase Detector
IF LD IF Charge Pump CPoIF
Figure 1. BLOCK DIAGRAM
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
BLOCK DIAGRAM- Continued
KB8821/22/23
VDD1 1
RF LD
foLD Data Out Multiplexer
IF LD
20 VDD2
VP1 2
RF Charge Pump
RF Phase Detector
IF Phase Detector
IF Charge Pump
19 VP2
CPoRF 3 RF Prescaler GND 4 + finRF 5 - Prescaler Control RF Programmable Counter IF Programmable Counter Prescaler Control - + IF Prescaler
18 CPoIF
17 GND
16 finIF
finRF 6 RF N-Latch GND 7 IF N-Latch 20-bit Shift Register RF R-Latch IF R-Latch 2-bit Control
15 finIF
14 GND
OSCin 8
13 LE
GND 9
RF Reference Counter
IF Reference Counter
12 DATA
foLD 10
11 CLOCK
Figure 2. Detailed block diagram
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PIN CONFIGURATION
KB8821/22/23
VDD1 1 Vp1 2 CPoRF 3 GND 4 (Digital) finRF 5
20 VDD2 19 Vp2 18 CPoIF 17 GND (Digital) 16 finIF
KB8821 KB8822
finRF 6
15 finIF
KB8823
GND 7 (Analog) OSCin 8 GND 9 (Digital) foLD 10 20-TSSOP
Top View
14 GND (Analog) 13 LE 12 DATA 11 CLOCK
20-Lead(0.173 Wide) Thin Shrink Small Outline Package(20-TSSOP)
1. pin #9 = pin #17(internally connected). 2. Do not tie up Vp and VDD : Vp is the source of digital noises. The power for analog part is supplied by VDD. If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PIN DESCRIPTION
Pin No 1 Symbol VDD1 I/O Description
KB8821/22/23
Power supply voltage input for the RF PLL part. V DD1 must equal VDD2. In order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane. Power supply voltage input for RF charge pump( VDD1). Internal RF charge pump output for connection to an external loop filter whose filtered output drives an external VCO. Ground for RF digital blocks. RF prescaler input. The signal comes from the external VCO. The complementary input of the RF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. Ground for RF analog blocks. Reference counter input. TCXO is connected via a coupling capacitor. Ground for IF digital blocks. Multiplexed output of the RF/IF programmable counters, the reference counters, the lock detect signals and the shift registers. The output level is CMOS level. (see fout Programmable Truth Table) CMOS clock input. Serial data for the various counters is transfered into the 22-bit shift register on the rising edge of the clock signal. Binary serial data input. The MSB of CMOS input data is entered first. The control bits are on the last two bits. CMOS input. Load enable CMOS input. When LE becomes high, the data in the shift register is loaded into one of the four latches(by the control bits). Ground for IF analog blocks. The complementary input of the IF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. IF prescaler input. The signal comes from the external VCO. Ground for IF digital blocks. Internal IF charge pump output for connection to an external loop filter whose filtered output drives an external VCO. Power supply voltage input for IF charge pump( VDD2) Power supply voltage input for the IF PLL part. V DD1 must equal VDD2. In order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane.
2 3 4 5 6
Vp1 CPoRF GND finRF finRF
O I I
7 8 9 10
GND OSCin GND
I O
foLD
11 12 13 14 15
CLOCK DATA LE GND finIF
I I I I
16 17 18 19 20
finIF GND CPoIF Vp2 VDD2
I O -
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
EQUIVALENT CIRCUIT DIAGRAM
CLOCK, DATA, LE foLD
KB8821/22/23
OSCin
CPoRF, CPoIF
finRF, finRF, finIF, finIF
finRF, finIF
finRF, finIF
Vbias
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Characteristic Power Supply Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD PD Ta TSTG Value 5.5 600 -40C ~ +85oC -65C ~ +150oC
KB8821/22/23
Unit V mW C C
ELECTROSTATIC CHARACTERISTICS
Characteristic Human Body Model Machine Model Charged Device Model Pin No. All All All ESD level < 2000 < 300 < 800 Unit V V V
** These devices are ESD sensitive. These devices must be handled in the ESD protected environment.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40CTa85C
Characteristic Symbol VDD Power Supply Voltage VP KB8823 RF + IF KB8823 RF Only Power Supply Current KB8822 RF + IF KB8822 RF Only KB8821 RF + IF KB8821 RF Only KB882x IF Only Power down Current IPWDN VDD=3.0V IDD VDD=2.7V to 4.0V VDD 3.0 5.5 4.0 4.5 3.0 3.5 2.0 1.5 1.0 Test Conditions
KB8821/22/23
Unless otherwise specified)
Min. 2.7
Typ. 3.0
Max. 4.0
Unit
V 4.0
mA
10
A
Digital inputs : CLOCK, DATA and LE High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Reference Divider Input : OSCin IIHR Input Current IILR Digital Output : foLD High Level Output Voltage Low Level Output Voltage VOH VOL Iout = -500A Iout = +500A
VDD-0.4
VIH VIL IIH IIL
VDD=2.7V to 4.0V VDD=2.7V to 4.0V VIH= VDD=4.0V VIL=0V, VDD=4.0V
0.7VDD 0.3VDD -1.0 -1.0 +1.0 +1.0
V V A A
VIH= VDD=4.0V VIL=0V, VDD=4.0V -100
+100
A A
V 0.4 V
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40CTa85C
Characteristic Symbol Test Conditions
KB8821/22/23
Unless otherwise specified)- Continued
Min.
Typ.
Max.
Unit
Charge Pump Outputs : CPoRF, CPoIF ICP-SRC ICP-SINK Charge Pump Output Current ICP-SRC ICP-SINK Charge Pump Leakage Current ICPL ICP-SINK vs ICP-SRC
ICP vs T
VCP=VP/2, ICPo=Low VCP=VP/2, ICPo=Low VCP=VP/2, ICPo=High VCP=VP/2, ICPo=High 0.5V VCP VP-0.5V VCP=VP/2 Ta=25oC VCP=VP/2 0.5V VCP VP-0.5V Ta=25oC -2.5
-1.125 +1.125 -4.5 +4.5 +2.5 nA mA
Output Current Sink vs. Source Mismatch* Output Current Magnitude Variation vs. Temperature** Output Current Magnitude Variation vs. Voltage*** Programmable Divider KB8823 Operating Frequency KB8822 KB8821 Operating Frequency
3
10
%
10
%
ICP vs VCP
10
15
%
0.5 finRF VDD=2.7V to 4.0V 0.2 0.1 finIF VDD=3.0V VDD=3.0V 45 -15 -10 -10
2.5 2.0 1.2 520 0 dBm 0 0 10 dBm MHz MHz GHz
RF Input Sensitivity IF Input Sensitivity Phase Detector Frequency Reference Divider Operating Frequency Input Sensitivity
PfinRF PfinIF fPD
VDD=4.0V VDD=2.7V to 4.0V
OSCin VOSCin
5 0.5
40
MHz VPP
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40CTa85C
Characteristic Serial Data Control CLOCK Frequency CLOCK Pulse Width High CLOCK Pulse Width Low DATA Set Up Time to CLOCK Risng Edge DATA Hold Time after CLOCK Rising Edge LE Pulse Width CLOCK Rising Edge to LE Rising Edge fCLOCK tCWH tCWL tDS tDH tLEW tCLE 50 50 50 10 50 50 Symbol Test Conditions
KB8821/22/23
Unless otherwise specified)- Continued
Min.
Typ.
Max.
Unit
10
MHz ns ns ns ns ns ns

Ia=Charge pump sink current at Vcp=Vp-V, Ib=Charge pump sink current at Vcp=Vp/2, I =Charge pump sink current at Vcp=V c Id=Charge pump source current at Vcp=VpV, Ie=Charge pump source current at Vcp=Vp/2, I=Charge pump source current at Vcp=V f V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents bec ome flat. * Output Current Sink vs. Source Mismatch = [| I |-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%) b ** Output Current Magnitude Variation vs. Temperature = [| Ib @any temp.| - |Ib @ 25C|] / | Ib @ 25C| * 100 (%) and [|Ie @any temp.| - |Ie @ 25C|] / |Ie @ 25C| * 100 (%) *** Output Current Magnitude Variation vs. Voltage = [0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%)
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
KB8821/22/23
The Samsung KB882x are dual PLL frequency synthesizer ICs. KB882x combined with external LPFs and external VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter, prescaler, phase detector, charge pump, and etc.(Figure 1). Serial data is moved into 20-bit shift register on the rising edge of the clock(Figure 2). These data enters MSB first. When LE becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control). The divide ratios of the prescaler and the counters are determined by the data stored in the latches. The external VCO output signal is divided by the prescaler and the N counter. External reference signal is divided by the R counter. These two signals are the two input signals to the phase detector. The phase detector drives the charge pump by comparing frequencies and phases of the above two signals.The charge pump and the external LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal.
Serial Data Input Timing MSB DATA N20(R20) N19(R19) N10(R10) N9(R9) C2 C1 LSB
CLOCK tCWL tCWH tLEW
tDS LE tDH
tCLE
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION Continued Control Bits Control Bits C1 0 0 1 1 C2 0 1 0 1
KB8821/22/23
DATA Location IF R Counter RF R Counter IF N Counter RF N Counter
Programmable Reference Counter(IF / RF R Counter) If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets the reference counter. Serial data format is shown in the table below.
LSB
C1 C2
MSB
R 2 R 3 R 4 R 5 R 6 R 7 R 8 R 9 R 10 R 11 R 12 R 13 R 14 R 15 R 16 R 17 R 18 R 19 R 20
R 1
Division Ratio of the R Counter, R Control Bits 15-Bit Programmable Reference Counter Ratio Division Ratio 3 4 * 32767 R 15 0 0 * 1 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1
Program Mo es d
R 4 0 0 * 1
R 3 0 1 * 1
R 2 1 0 * 1
R 1 1 0 * 1
Division ratio : 3 to 32767 Data are shifted in MSB first
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION Continued -
KB8821/22/23
Programmable Counter(N Counter) If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown below. LSB
C1 C2
MSB
N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 N 10 N 11 N 12 N 13 N 14 N 15 N 16 N 17 N 18 N 19 N 20
N 1
Division Ratio of the N Counter, N Control Bits 7-Bit Swallow Counter Division Ratio(A Counter) RF Division Ratio(A) 0 1 * 127 N 7 0 0 * 1 N 6 0 0 * 1 N 5 0 0 * 1 N 4 0 0 * 1 N 3 0 0 * 1 N 2 0 0 * 1 N 1 0 1 * 1 Division Ratio(A) 0 1 * 15 N 7 X X * X IF N 6 X X * X N 5 X X * X N 4 0 0 * 1 N 3 0 0 * 1 N 2 0 0 * 1 N 1 0 1 * 1 Program Modes
Division ratio : 0 to 127 B A 11-Bit Main Counter Division Ratio(B Counter) Division Ratio 3 4 * 2047 N 18 0 0 * 1 N 17 0 0 * 1 N 16 0 0 * 1 N 15 0 0 * 1 N 14 0 0 * 1 N 13 0 0 * 1 N 12 0 0 * 1
Division ratio : 0 to 15 B A X = DON CARE condition 'T
N 11 0 0 * 1
N 10 0 1 * 1
N 9 1 0 * 1
N 8 1 0 * 1
Division ratio : 3 to 2047
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION Continued Pulse Swallow Function fVCO=[ ( P X B ) + A ] x fOSCin / R fVCO : External VCO output frequency P : Preset modulus of dual modulus prescaler (for KB8821/22 RF:P=64 or 128, for KB8823 RF:P=32 or 64, for IF: P=8 or 16) B : 11-bit main counter division ratio (3 B 2047) A : 7-bit swallow counter division ratio (for RF: 0 127, for IF: 0 15, B)
KB8821/22/23
fOSCin : External reference frequency(from external oscillator) R : 15-bit reference counter division ratio (3 R 32767)
Program Mode C1 0 0 C2 0 1 R16 IF Phase Detector Polarity RF Phase Detector Polarity R17 IF ICPo RF ICPo R18 IF CPoIF High Impedance RF CPoIF High Impedance R19 IF LD RF LD R20 IF Fo RF Fo
C1 1 1
C2 0 1
N19 IF Prescaler RF Prescaler
N20 Pwdn IF Pwdn RF
Mode Select Truth Table RF Prescaler KB8821/22 (KB8823) 64/65 (32/33) 128/129 (64/65)
Phase Detector Polarity 0 1 Negative Positive
CPoIF High Impedance Normal Operation High Impedance
ICPo Low High
IF Prescaler 8/9 16/17
Pwdn Pwr Up Pwr Dn
* The charge pump output current of I CPo LOW = 1/4 x ICPo HIGH.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION Continued Phase Detector Polarity Depending on VCO characteristics, R16 bit should be set as follows : VCO characteristics are positive like (1) : R16 HIGH VCO characteristics are negative like (2) : R16 LOW
VCO Output Frequency
KB8821/22/23
VCO Characteristics (1)
(2)
VCO Input Voltage
foLD (Pin10) Output Truth Table RF R19 (RF LD) 0 0 1 1 0 0 0 0 0 0 1 1 IF R19 (IF LD) 0 1 0 1 0 0 1 1 0 1 0 1 RF R20 (RF fo) 0 0 0 0 0 1 0 1 1 1 1 1 IF R20 (IF fo) 0 0 0 0 1 0 1 0 1 1 1 1 foLD Output State Disabled (default LOW) IF Lock Detect RF Lock Detect RF and IF Lock Detect IF Reference Divider Output RF Reference Divider Output IF Programmable Divider Output RF Programmable Divider Output High Speed Lock mode IF Counter Reset RF Counter Reset RF and IF Counter Reset
- When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses LOW. - Counter Reset mode resets R & N counters. - The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance (110).
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION Continued -
KB8821/22/23
Powerdown mode operation There are synchronous and asynchronous powerdown modes for KB8821/22/23. Synchronous powerdown mode occurs if R18 bit is LOW, N20 bit is HIGH and charge pump output is in high impedance state. In the synchronous power down mode, the powerdown function is activated by the charge pump to diminish unwanted frequency jumps. Asynchronous powerdown mode occurs if R18 bit is HIGH and N20 bit is HIGH. When the PLL goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, R & N counters keeps their load conditions and the charge pump becomes high impedance state. The oscillator circuitry function becomes disabled only when both IF and RF powerdown bits are activated, i.e. N20 HIGH. The PLL returns to an active powerup mode when N20 bit becomes LOW(either in synchronous or asynchronous modes). R18 0 1 0 1 N20 0 0 1 1 PLL active PLL active, only charge pump high impedance Synchronous powerdown Asynchronous powerdown Powerdown mode status
Phase Detector and Charge pump Characteristics
Phase difference detection range : -2 ~ +2 When R16 = HIGH
fr
fp
LD
CPo fr>fp fr=fp fr99-06-15
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
RF SENSITIVITY MEASUREMENT CIRCUIT
KB8821/22/23
2.7V ~ 4.0V 50 Microstrip
10dB ATTN
RF Signal Generator
100pF
VDD fin fin OSCin LE foLD DATA CLOCK PC Parallel Port VP 100pF 2.2F 100pF 2.2F
100pF 51
Frequency
Counter
12k 39k
** N=10,000 R=50 P=64 ** Sensitivity limit is determined when the error of the divided RF output( foLD) becomes 1 Hz.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
TYPICAL APPLICATION CIRCUIT
KB8821/22/23
VP VCO Reference Input 51 foLD 100pF Rin 10 foLD 9 GND 8 OSCin 7 GND 6 finRF 5 finRF 4 GND 3 CPoRF 2 VP1 18 1000pF RF out 10pF C2 100pF 0.01F R1 C1 100pF
100pF
VDD 0.01F
1 VDD1
0.01F
KB882x 20-TSSOP
CLOCK DATA 11 From Controller IF out 10pF 12 LE 13 GND 14 finIF 15 finIF 16 Rin 100pF VCO Vp R2 C3 C4 100pF 0.01F 100pF GND 17 CPoIF 18 VP2 19 VDD2 20 0.01F 18 VDD 0.01F
100pF
** The role of Rin : Rin makes VCO output power go to the load rather than the PLL. The value of Rin depends on the VCO power level.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PACKAGE DIMENSIONS
KB8821/22/23
#20
#11 4.40 3/4 0.20 0.173 3/4 0.008 0.15 x +0.10 -0.05
0.006 x +0.004 -0.002
6.40 0.30 0.252 0.012
0 ~ 8o
5.72 0.225 0.50 3/4 0.20 0.020 3/4 0.008
#1
#10
0.90 0.20 0.059 0.008
6.40 3/4 0.20 0.252 3/4 0.008
1.10 0.073 MAX
6.90 MAX 0.272
0.10MAX 0.004MAX 0.05 0.002 MIN
0.30 0.012 0.22 3/4 0.10 0.009 3/4 0.004
0.65 0.026
20-Lead TSSOP Package (Samsung 20-TSSOP-225)
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
Addendum(for 24-QFN package) PIN CONFIGURATION(24-QFN, not to scale)
VDD1 VDD2 Vp2 N/C Vp1 CPoRF GND (Digital) finRF finRF 1 2 3 4 5 6 24 23 22 21 20 19 N/C CPoIF GND (Digital) finIF finIF GND (Analog) LE DATA N/C
KB8821/22/23
KB8821 KB8822 KB8823 Top View
18 17 16 15 14
GND 7 (Analog) OSCin N/C 8 9 10 11 12
13
GND foLD CLOCK (Digital)
* N/C pins must be connected to GND(to Analog GND if possible).
24-QFN 24 PIN Quad Flat Non-leaded (24-QFN) Package
1. pin #10 = pin #19(internally connected). 2. Do not tie up Vp and VDD : Vp is the source of digital noises. The power for analog part is supplied by VDD. If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.
TEL-97-D003 99-06-15
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PIN DESCRIPTION(24-QFN)
Pin No ( 20TSSOP) Pin No (24QFN)
KB8821/22/23
Symbol
I/O -
Description Power supply voltage input for the RF PLL part. V DD1 must equal VDD2. In order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane. No connection. Power supply voltage input for RF charge pump( VDD1). Internal RF charge pump output for connection to an external loop filter whose filtered output drives an external VCO. Ground for RF digital blocks. RF prescaler input. The signal comes from the external VCO. The complementary input of the RF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. Ground for RF analog blocks. Reference counter input. TCXO is connected via a coupling capacitor. No connection. Ground for IF digital blocks. Multiplexed output of the RF/IF programmable counters, the reference counters, the lock detect signals and the shift registers. The output level is CMOS level. (see fout Programmable Truth Table) CMOS clock input. Serial data for the various counters is transfered into the 22-bit shift register on the rising edge of the clock signal. No connection. Binary serial data input. The MSB of CMOS input data is entered first. The control bits are on the last two bits. CMOS input. Load enable CMOS input. When LE becomes high, the data in the shift register is loaded into one of the four latches(by the control bits). Ground for IF analog blocks. The complementary input of the IF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. IF prescaler input. The signal comes from the external VCO. Ground for IF digital blocks. Internal IF charge pump output for connection to an external loop filter whose filtered output drives an external VCO. No connection. Power supply voltage input for IF charge pump( VDD2)
1
24
VDD1
2 3 4 5 6
1 2 3 4 5 6
Vp1 CPoRF GND finRF finRF
N/C O I I
7 8 9 10
7 8 9 10 11
GND OSCin GND
I N/C O
foLD
CLOCK DATA
11 12
12 13 14
I N/C I
13 14 15
15 16 17
LE GND finIF
I I
16 17 18 19
18 19 20 21 22
finIF GND CPoIF Vp2
I O N/C -
TEL-97-D003 99-06-15
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
20 23 VDD2 -
KB8821/22/23
Power supply voltage input for the IF PLL part. V DD1 must equal VDD2. In order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane.
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